The present invention relates to the field of MOS transistors manufactured in a thin silicon layer formed on an insulating substrate.
In Silicon On Insulator (SOI) technology, elementary transistors are formed in portions of a monocrystalline silicon layer formed on an insulating substrate. Two main types of SOI technologies can be differentiated according to the way in which the individual transistors are insulated one from the other.
According to a first technology, each of the MOS transistors is formed in a mesa of the thin monocrystalline silicon layer, with each mesa being separated from the others by removal of the thin silicon layer.
According to a second technology, regions the transistors are formed are separated from each other by a dielectric insulation, generally formed by oxidizing the entire thin layer except regions where the transistors are to be formed.
First, the state of the prior art and the present invention are described for the case of mesa-type technology; then, a variant of the invention is disclosed for dielectric insulation technology.
FIGS. 1A and 1B are a sectional and top views of a conventional MOS transistor formed on a silicon on insulator structure (FIG. 1A being a section view along line A--A of FIG. 1B).
As shown in FIGS. 1A and 1B, such a structure is formed from a thin monocrystalline silicon layer on insulating substrate 1. This thin silicon layer is etched to leave in place only a block, having a central portion corresponding to a low doped substrate 3 of a first conductivity type, here P-type, lowly doped in the upper portion where a channel is to be formed; outer regions of the block correspond to source 5 and a drain 6, both highly N.sup.+ doped to be, of an opposite conductivity type from the substrate. A conductive electrode in the form of gate 7 is formed above substrate channel region 3. Insulating layer 8 is interposed between gate 7 end region 3. Usually, gate 7 is made of polycrystalline silicon and the gate insulator 8 of silicon oxide. In the conventional structure, insulating spacers 9, usually made of silicon oxide or silicon nitride, are formed on both sides of gate 7 and serve, on the one hand, to implant the drain and source according to the represented shape, that is, more deeply penetrating under the gate in their upper portion and, on the other hand, to ensure insulation between the gate contact 7 and the drain and source contacts, represented as crosses surrounded by squares in the top view of FIG. 1B.
Moreover, as known in the field of MOS transistor utilization, it is desirable to provide a contact between substrate or channel region 3 and source region 5 to avoid various parasitic effects, namely:
1) a "kink" effect associated with the presence of a floating substrate channel region 3 when the silicon on insulator layer is too thick and/or too highly doped (this effect appears in the form of a bump on the drain-current/drain-voltage characteristic);
2) the occurrence of a parasitic bipolar transistor which introduces hysteresis in the transistor current-voltage characteristics; and
3) the occurrence of a parasitic edge transistor associated with the lateral insulation.
To form such a contact between the substrate and the source, the conventional method such as illustrated in FIG. 1B, consists in (1) providing an extension 10 of the monocrystalline silicon portion corresponding to the substrate or channel 3, and (2) forming a contact on extension 10, the contact being connected through a metallization to the contact of source 5. Extension 10 must be doped with the same conductivity type as dopant substrate that of, but with a higher doping level (P.sup.+ in the given example). The drawback of this conventional structure is that it increases the surface of each elementary transistor. With present technologies, the surface area necessary for a contact is substantially of the same order of magnitude as the areas of the source, drain or channel of a transistor. By way of example, in a prior art implementation, the thickness of the monocrystalline silicon layer is about 200 nm and each rectangular transistor block has sides of about 2000.times.5000 nm; the sides of region 10, the only function of which is to establish a contact, must be about 2000.times.2000 nm. Moreover, an access resistor between this contact and the substrate becomes prohibitive as the sizes of the transistors decrease.
An object of the invention is to provide a new and improved MOS SOI transistor structure, wherein contact is between the channel and source is provided, without substantially increasing the transistor surface area.
Another object of the invention is to provide a specific method of manufacturing such a structure as an SIO mesa-type MOS transistor.
A further object of the invention is to provide a specific method of manufacturing such a structure as a dielectrically insulated SOI MOS transistor.